In many cases, semiconductor circuit devices utilizes internal voltages different in voltage level from a power supply voltage and the ground voltage. Such internal voltages include a boosted voltage higher than the power supply voltage and a negative voltage lower than the ground voltage. In a DRAM (Dynamic Random Access Memory), generally the boosted voltage is used to drive a selected word line, while the negative voltage is used to bias a substrate of a memory array to stabilize a threshold voltage of a memory cell transistor and reduce a parasitic capacitance. In the DRAM, the negative voltage is utilized, in some cases, to maintain a non-selected word line at a non-selected state.
In a non-volatile memory such as a flash memory, the boosted voltage and the negative voltage are utilized to program/erase data. Memory transistors according to different write/erase schemes receives at different nodes the boosted voltage and the negative voltage.
The boosted voltage and the negative voltage are also utilized to drive the gate of a pixel transistor in a liquid crystal display unit.
These internal voltages are generated within a semiconductor circuit device to reduce the number of pin terminals and current consumption in the entire system. As a circuit for producing such internal voltage, generally a charge pump circuit utilizing a charge pump operation of a capacitor is widely employed.
FIG. 1 shows an example of the configuration of a conventional internal voltage generation circuit for producing a negative voltage. In FIG. 1, the internal voltage generation circuit includes a charge pump circuit 100 utilizing a charge pump operation of a capacitive element to generate the negative voltage when active, a voltage detection circuit 102 for detecting a voltage level of an output node 9 of charge pump circuit 100 and producing a signal indicating a result of detection, and a charge pump control circuit 101 for selectively activating charge pump circuit 100 in accordance with the output signal from voltage detection circuit 102.
The charge pump circuit typically includes at least one capacitive element for charge pumping and at least two uni-directional elements (rectifying elements). At least two uni-directional elements each have a rectifying function and supply charge only in one direction. These at least two uni-directional elements are required to draw charge from the output node and precharge an internal node for charge accumulation.
In FIG. 1, charge pump circuit 100 includes a capacitive element 5 connected between nodes 4 and 8, an N channel MOS transistor (insulated gate field effect transistor) 6 connected between node 8 and the ground node and having its gate connected to node 8, and an N channel MOS transistor 7 connected between node 8 and an output node 9 and having its gate connected to output node 9. MOS transistors 6 and 7 each have the gate and drain connected together and operate as a diode (uni-directional element).
Voltage detection circuit 102 includes a resistance element 13 of high resistance connected between a power supply node 2 and a node 14, and N channel MOS transistors 10 and 12 connected in series between node 14 and output node 9 of charge pump circuit 100. MOS transistor 10 has its one conduction node (source) connected to output node 9 of charge pump circuit 100 and its gate and drain connected to a node 11. MOS transistor 12 has its source connected to node 11, its drain connected to node 14, and its gate connected to the ground node.
Charge pump control circuit 101 includes a two-input AND circuit 3 receiving a repetition signal (pump clock signal) φ applied to a clock node 1 and a signal from node 14 of voltage detection circuit 102. AND circuit 3 applies the charge pumping clock signal (repetition signal) via node 4 to charge pump circuit 100.
FIG. 2 is a signal waveform diagram representing an operation of the internal voltage generation circuit shown in FIG. 1. The operation of the internal voltage generation circuit shown in FIG. 1 will now be described with reference to FIG. 2. It is assumed here that MOS transistors 6, 7, 10, and 12 each have a threshold voltage, VTN. When a potential of node 14 is at a logically high (H) level, that is, when at least one of MOS transistors 10 and 12 is off, AND circuit 3 in charge pump control circuit 101 operates as a buffer circuit and transmits repetition signal φ applied to clock node 1 to node 4.
In accordance with the repetition signal applied to node 4, capacitive element 5 performs the charge pump operation and changes the potential of node 8. Specifically, when repetition signal φ rises to the H level, the charge pump operation of capacitive element 5 increases the voltage level of node 8. When the voltage level of node 8 increases, MOS transistor 6 conducts to clamp the voltage level of node 8 at its threshold voltage VTN level. At this stage, the voltage level of output node 9 is not higher than the ground voltage level, and MOS transistor 7 is kept off.
When repetition signal φ falls down to the L level, the charge pump operation of capacitive element 5 decreases the voltage level of node 8. When an amplitude of the voltage at node 4, determined by repetition signal φ, is VDD, the voltage level of node 8 is lowered to the voltage level of VTN−VDD. In this state, MOS transistor 6 is off. In contrast, MOS transistor 7 conducts when output node 9 is at a voltage level not lower than 2·VTN−VDD. Responsively, positive charges are supplied from output node 9 to node 8, and the voltage level of output node 9 decreases.
By repeating the above-described operation, positive charges are drawn from output node 9, whereby the voltage level of output node 9 decreases. Charge pump circuit 100 is capable of generating a voltage V9, as expressed below, at output node 9.V9=−VDD+2·VTN  (1)
As for voltage detection circuit 102, when the difference between voltage V9 of node 9 and the voltage of node 11 is VTN or more, MOS transistor 10 conducts. In addition, MOS transistor 12 receives the ground voltage at its gate, and conducts when the voltage level of node 11 is not higher than −VTN. Therefore, when the voltage from charge pump circuit 100 attains the level of −2·VTN, MOS transistors 10 and 12 conduct, and accordingly the voltage level of node 14 decreases. Specifically, both MOS transistors 10 and 12 in voltage detection circuit 102 conduct when the following voltage condition is satisfied.
                                                        V9              =                            ⁢                              VG12                -                VTN12                -                VTN10                                                                                        =                            ⁢                              0                -                VTN                -                VTN                                                                                        =                            ⁢                                                -                  2                                ·                VTN                                                                        (        2        )            
Here, VG12 represents a gate voltage of MOS transistor 12. VTN10 and VTN12 are threshold voltages of MOS transistors 10 and 12, respectively, and they are equal to voltage VTN.
When on-resistances (channel resistances) of MOS transistors 10 and 12 are set to be sufficiently smaller than a resistance value of resistance element 13 of high resistance, the voltage level of node 14 attains L level if both MOS transistors 10 and 12 conduct. As a result, the output signal from AND circuit 3 in charge pump control circuit 101 is fixed at the L level, and the pump operation of charge pump circuit 100 halts. Therefore, voltage V9 of output node 9 of charge pump circuit 100 is maintained at −2·VTN.
As shown in FIG. 1, by employing MOS transistors 10 and 12 as voltage level detecting elements in voltage detection circuit 102, charge pump circuit 100 can selectively be activated in accordance with the voltage level of output node 9 of charge pump circuit 100, and internal voltage V9, at a level according to a voltage level detected by voltage level detection circuit 102, can be generated.
As represented in the above expression (2), however, the detected voltage level of voltage V9 from output node 9 is −2·VTN, and is determined by the threshold voltages of the MOS transistors. Therefore, if the threshold voltages of MOS transistors 10 and 12 vary, the variation in threshold voltage of MOS transistors 10 and 12 directly influences the detected voltage level. Specifically, if the threshold voltages of MOS transistors 10 and 12 each vary by ΔV, the detected voltage level varies by 2·ΔV. Therefore, the circuit utilizing the internal voltage generated by charge pump circuit 100 suffers from a disadvantage that the internal voltage level varies to reduce an operating margin.
Particularly, in a liquid crystal display device or the like containing a low-temperature polysilicon TFT circuit, variation in threshold voltage of the TFT (Thin Film Transistor) is large since a low-temperature processing is applied in view of protection of the substrate glass and thus polysilicon and a gate insulator film cannot sufficiently be annealed. In the case of generating an internal voltage for driving a switching transistor of an active matrix element in such liquid crystal display devices, if a low-temperature polysilicon TFT similar to the active matrix element is used for detection of the level of the internal voltage, the detected voltage level would significantly vary, and the active matrix element cannot accurately be driven AC-wise (switching transistor cannot be driven with a symmetrical waveform supplied to the gate).
The problem of the influence of threshold voltage on the detected voltage level for a negative voltage generated as the internal voltage as described above, when the negative voltage is generated as the internal voltage, the detected level of the negative voltage is influenced by the threshold voltage, similarly arises when a similar detection circuit is employed in the case of generating a boosted voltage by means of the charge pump circuit.
Moreover, when the voltage detection circuit shown in FIG. 1 is employed, its detecting voltage level is determined by an integer multiple of threshold voltage VTN of MOS transistors 10 and 12. Therefore, the voltage level of the internal voltage that can be generated, is set on the basis of a step of a threshold voltage of the MOS transistor, so that the internal voltage cannot be produced at a desired voltage level. Therefore, a problem arises that an internal voltage greater in absolute value than necessary may be generated to degrade the reliability of an element. When the voltage level of the internal voltage is determined by the threshold voltage of the MOS transistor, typically, threshold voltage VTN is on the order of 0.6V, and therefore, the influence on the reliability of the element will be more significant in a low power supply voltage environment in which the operating power supply voltage is as low as 1.8V to 1.5V.